Andrey Semashev
07be21c7e8
Silenced some MSVC warnings.
2016-11-06 21:29:33 +03:00
Andrey Semashev
836381dcd1
Added workarounds for Oracle Studio 12.5 on x86.
2016-10-09 19:15:42 +03:00
Andrey Semashev
336a349b9f
Added is_always_lock_free static constant from C++17.
2016-10-09 17:53:55 +03:00
Andrey Semashev
e450653451
Extracted x86 mfence detection to caps headers.
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Also, for non-gcc compilers which do not allow to auto-detect mfence availability (e.g. Oracle Studio) the instruction is assumed to be supported (since SSE2 is supported by virtually every x86 CPU now). This can be changed by defining BOOST_ATOMIC_NO_MFENCE.
2016-09-15 01:05:51 +03:00
Andrey Semashev
dce87d3c0a
Changes for better compatibility with Oracle Studio 12.5.
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1. Although the compiler is supposed to support __atomic and __sync intrinsics like gcc, it does not define any macros allowing to detect that. In particular, it is not possible to deduce what sizes of atomic operands are supported in hardware except to check the arch macros.
2. The compiler does not define any macros that allow to deduce the target x86 CPU, which makes it impossible to know whether the CPU supports cmpxchg8b/cmpxchg16b/mfence.
Because of that this commit changes handling of this compiler the following way:
1. On SPARC the compiler will use the gcc_sparc backend. Also, enabled the backend for the SPARCv8+ architecture as it appears to be almost a 32-bit equivalent to SPARCv9 and does support cas/casx instructions.
2. On x86 the compiler will use the gcc_x86 backend. By default cmpxchg8b/cmpxchg16b are assumed to be supported unless BOOST_ATOMIC_NO_CMPXCHG8B/BOOST_ATOMIC_NO_CMPXCHG16B is defined. The mfence instruction requires SSE2 and although ubiquitous these days, it will still be detected as not supported for now.
2016-09-15 00:46:26 +03:00
Andrey Semashev
4274a78f46
Corrected typos that prevented compilation.
2016-09-14 20:36:12 +03:00
Jeremy W. Murphy
0abd9bfd73
Fix some unused parameter warnings.
2015-12-15 20:56:58 +11:00
Andrey Semashev
430169a53c
Removed union_cast in favor of memcpy-based implementation and renamed the cast to bitwise_cast. Use __builtin_mem* instead of regular function calls when possible. This saves inclusion of <cstring> and possibly generates better code when -fno-builtin is used. The net result of these changes is no UB that union_cast was introducing while hopefully retaining the same performance.
2015-12-02 20:04:10 +03:00
Andrey Semashev
c989d936c5
Renamed casts.hpp to bitwise_cast.hpp.
2015-12-02 18:36:49 +03:00
Andrey Semashev
8bbf5e19db
Corrected compiler check for BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS.
2015-11-08 17:24:30 +03:00
Andrey Semashev
6e2d7b28de
Restored old versions of DCAS operations that use an extra register for compatibility with old binutils, which apparently are used on OS X with gcc 4.2.
2015-11-04 15:25:12 +03:00
Andrey Semashev
ec4738a8eb
Workaround for MSVC-12 ICE.
2015-08-26 23:27:13 +03:00
Andrey Semashev
e3aac4bc65
Simplified memory references in assembler blocks which should reduce the typical number of used registers by one.
2015-08-23 03:27:37 +03:00
Andrey Semashev
4462c1cdf4
Fixed compilation with gcc 4.4.
2015-08-23 02:05:35 +03:00
Andrey Semashev
18fdcb1747
Fixed compilation errors with MSVC caused by using types with large alignment values as function arguments. Alignment is now explicitly specified for all storage types to avoid surprises. Optimized CAS-based exchange implementation on x86. Relaxed initial loads in CAS-based operations as this load is not required to be accurate.
2015-08-23 01:04:08 +03:00
Tim Blechmann
f0f1ef228c
atomic: fix compilation on msvc 8 / Windows CE / arm
2015-08-22 10:17:02 +02:00
Andrey Semashev
ff91811c1a
Fixes #10994 . Fixed compilation with gcc 4.4 when cmpxchg16b is used.
2015-08-17 23:27:37 +03:00
Andrey Semashev
a8661d4cc2
Corrected memory barriers in store, load and thread_fence. Added indentation to the generated assembler code.
2015-08-15 00:29:43 +03:00
Andrey Semashev
e6a188d165
Experimental support for IBM XL C++ compilers for PowerPC.
2015-08-13 23:37:33 +03:00
Andrey Semashev
fcff86225e
Added workarounds for nvcc - don't use cc clobber and constraint alternatives in asm statements. Hopefully, should fix #10625 .
2014-12-20 16:35:03 +03:00
Andrey Semashev
fe8f1dc4e0
Use #pragma intrinsic only with MSVC.
2014-10-01 13:30:37 +04:00
Andrey Semashev
5f6e9689a3
Silenced MSVC warnings about unused parameters.
2014-10-01 13:02:15 +04:00
Andrey Semashev
415db70547
Added support for extending operations to GCC atomic backend.
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Fix for #10446 . Some platforms (e.g. Raspberry Pi) only support atomic ops of some particular size but not less. Use extending arithmetic operations for these platforms. Also, make sure bools are always treated as 8-bit values, even if the actual type is larger. This makes its use in atomic<>, atomic_flag and lock pool more consistent.
2014-09-27 20:40:09 +04:00
Andrey Semashev
8f10f20359
Use #pragma intrinsic only with MSVC.
2014-08-30 14:09:18 +04:00
Andrey Semashev
7f17e3b9a3
Use #pragma intrinsic only with MSVC.
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Intel compiler doesn't support and doesn't need #pragma intrinsic and
issues warnings about it. Based on changes to boost/detail/
2014-08-24 00:02:16 +04:00
Andrey Semashev
4dee330229
Added support for types with non-trivial default constructors.
2014-07-07 22:40:41 +04:00
Andrey Semashev
6a184d95dd
Renamed union_cast.hpp -> casts.hpp.
2014-07-07 21:51:06 +04:00
Andrey Semashev
00c2879066
Made sure that memory_order_consume is equivalent to memory_order_acquire on SPARC. Also make signal fences more strict in case of memory_order_consume since the standard requires them to be equivalent to thread fences except for thread synchronization instructions.
2014-07-07 21:48:53 +04:00
Andrey Semashev
0c9b1b3806
Reworked platform selection, fixed Windows backend.
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Platform selection now works in two stages. First compiler is tested for
the supported configuration. If that fails, OS is tested. Lastly, if
nothing succeeded, emulation backend is selected.
2014-06-09 01:07:26 +04:00
Andrey Semashev
b44027a58e
Removed dependency on Boost.Detail. Fixed compilation issues with MSVC
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7.1
2014-06-09 00:01:12 +04:00
Andrey Semashev
a6ec366f02
Fixed compilation failure due to a missing argument name.
2014-06-04 21:41:06 +04:00
Andrey Semashev
e0f038e92a
Fixed compilation failure due to a missing argument name.
2014-06-04 21:38:15 +04:00
Andrey Semashev
21e497c01b
Corrected hw memory barriers for memory_order_consume.
2014-06-03 23:57:52 +04:00
Andrey Semashev
d4ee3a3047
Added a comment about the reason why we promote memory_order_consume to memory_order_acquire.
2014-06-03 23:30:21 +04:00
Andrey Semashev
e55bf17309
Changed memory_order_consume handling on ARM and PPC.
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memory_order_consume is promoted to memory_order_acquire on these
architectures as they have a weaker memory model than other
architectures. GCC seems to behave the same way. Added nonessential
checks to compiler barriers so that the behavior is closer to thread
fences.
2014-06-01 20:03:53 +04:00
Andrey Semashev
abdce8f1bb
Changed memory_order constant values to simplify checks for success/failure orders in compare_exchange methods. Fixed incorrect cas_failure_order_must_not_be_stronger_than_success_order check.
2014-06-01 02:10:44 +04:00
Andrey Semashev
a721aa468f
Removed scratch argument for asm block in non-PIC mode.
2014-05-26 23:21:01 +04:00
Andrey Semashev
97ae84a474
Adjusted the workaround for ldrexd/strexd instruction problem with register pairs allocation. The problem only affects ARMv6k in Thumb mode, so enable these instructions for ARM mode. Also don't base the decision on the compiler version, it is probably not relevant. Updated lockfree test to reflect the recent changes related to ARM backends.
2014-05-23 21:02:07 +04:00
Andrey Semashev
deddca6918
Fixed a few bugs with ARM assembler: incorrect comparisons in compare_exchange, compilation failures due to insufficient registers in some optimization modes. Eventually I had to disable 64-bit atomic ops for gcc 4.7 because it is not able to allocate register pairs suitable for ldrexd/strexd instructions.
2014-05-22 01:01:46 +04:00
Andrey Semashev
a71a23694b
Fixed typo in a comment.
2014-05-21 00:36:43 +04:00
Andrey Semashev
7197b188ac
Another attempt to work around the problem with old binutils not supporting dmb arguments. Changed 64-bit operations so that the generated asm does not contain offsets in ldrexd and strexd instructions. Otherwise ARM assembler chokes.
2014-05-21 00:34:10 +04:00
Andrey Semashev
b8626e355b
Moving memory_order.hpp to Boost.Atomic.
2014-05-20 21:59:22 +04:00
Andrey Semashev
7f290018d2
Changed the dmb instruction argument in attempt to fix compilation with old binutils on QNX.
2014-05-18 19:03:55 +04:00
Andrey Semashev
76b78f2491
#9985 . Added ebx saves and restores in asm blocks to avoid frame pointer clobbering, when frame pointer omission is disabled.
2014-05-17 21:58:59 +04:00
Andrey Semashev
00c21f9978
Documented new feature test and configuration macros. Fixed disabled gcc atomic backend.
2014-05-17 19:20:51 +04:00
Andrey Semashev
08d30a2320
Added missing include.
2014-05-11 23:14:47 +04:00
Andrey Semashev
890313b8d7
Added missing include.
2014-05-11 23:13:58 +04:00
Andrey Semashev
3a81a36bbe
Removed no longer used files.
2014-05-11 20:28:12 +04:00
Andrey Semashev
5c032ccf3a
Added gcc Alpha backend. Completely untested.
2014-05-11 20:21:41 +04:00
Andrey Semashev
5cb6e92ed0
Extracted common c86 DCAS code to a separate header.
2014-05-11 17:33:09 +04:00
