mirror of
https://github.com/boostorg/atomic.git
synced 2026-02-02 08:22:08 +00:00
dce87d3c0a
1. Although the compiler is supposed to support __atomic and __sync intrinsics like gcc, it does not define any macros allowing to detect that. In particular, it is not possible to deduce what sizes of atomic operands are supported in hardware except to check the arch macros. 2. The compiler does not define any macros that allow to deduce the target x86 CPU, which makes it impossible to know whether the CPU supports cmpxchg8b/cmpxchg16b/mfence. Because of that this commit changes handling of this compiler the following way: 1. On SPARC the compiler will use the gcc_sparc backend. Also, enabled the backend for the SPARCv8+ architecture as it appears to be almost a 32-bit equivalent to SPARCv9 and does support cas/casx instructions. 2. On x86 the compiler will use the gcc_x86 backend. By default cmpxchg8b/cmpxchg16b are assumed to be supported unless BOOST_ATOMIC_NO_CMPXCHG8B/BOOST_ATOMIC_NO_CMPXCHG16B is defined. The mfence instruction requires SSE2 and although ubiquitous these days, it will still be detected as not supported for now.