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mfence is more expensive on most recent CPUs than a lock-prefixed instruction on a dummy location, while the latter is sufficient to implement sequential consistency on x86. Some performance test results are available here: https://shipilev.net/blog/2014/on-the-fence-with-dependencies/ Also, for seq_cst stores in gcc_atomic backend, use an xchg instead of mov+mfence, which are generated by gcc versions older than 10.1. The machinery to detect mfence presence is still left intact just in case if we need to use this instruction in the future. Closes https://github.com/boostorg/atomic/issues/36.
